The future of 32-bit Linux

The future of 32-bit Linux

I agree with most parts of your comment. However, just some notes:

• It is likely that the number of programmer-visible registers in future CPUs will be less relevant to performance than today:
  • Future CPUs will be able to process multiple L1D cache loads and stores per cycle
    • Year 2021: A fast x86 CPU core can process up to 3 L1D loads per cycle
  • A Zen 2 CPU core, or a Skylake CPU core, has 180 integer registers. Zen 2 integer reorder buffer size is 224 items. A Zen 3 CPU core has 192 integer registers.
    • The main question is how to extract more ILP (instruction-level parallelism) from a sequential instruction stream in order to maximize the utilization of those 180/192 integer registers.
  • A high-performance CPU core contains a data forwarding network bypassing the L1D cache
• I believe you might be putting too much emphasis on what the programmer sees (8 registers vs 16 registers), instead of putting emphasis on what the CPU is doing