| From: |
| Andrew Murray <andrew.murray-AT-arm.com> |
| To: |
| Catalin Marinas <catalin.marinas-AT-arm.com>, Will Deacon <will-AT-kernel.org>, Marc Zyngier <maz-AT-kernel.org>, Mark Rutland <mark.rutland-AT-arm.com> |
| Subject: |
| [PATCH v4 0/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters |
| Date: |
| Thu, 23 Jan 2020 11:58:49 +0000 |
| Message-ID: |
| <20200123115852.55595-1-andrew.murray@arm.com> |
| Cc: |
| kvmarm-AT-lists.cs.columbia.edu, linux-arm-kernel-AT-lists.infradead.org |
| Archive-link: |
| Article |
At present ARMv8 event counters are limited to 32-bits, though by
using the CHAIN event it's possible to combine adjacent counters to
achieve 64-bits. The perf config1:0 bit can be set to use such a
configuration.
With the introduction of ARMv8.5-PMU support, all event counters can
now be used as 64-bit counters. Let's add support for 64-bit event
counters.
As KVM doesn't yet support 64-bit event counters, we also trap
and emulate the Debug Feature Registers to limit the PMU version a
guest sees to PMUv3 for ARMv8.4.
Tested by running the following perf command on both guest and host
and ensuring that the figures are very similar:
perf stat -e armv8_pmuv3/inst_retired,long=1/ \
-e armv8_pmuv3/inst_retired,long=0/ -e cycles
Changes since v3:
- Rebased onto v5.5-rc7
- Instead of overriding trap access handler, update read_id_reg
Changes since v2:
- Rebased onto v5.5-rc4
- Mask 'cap' value to 'width' in cpuid_feature_cap_signed_field_width
Changes since v1:
- Rebased onto v5.5-rc1
Andrew Murray (3):
arm64: cpufeature: Extract capped fields
KVM: arm64: limit PMU version to ARMv8.4
arm64: perf: Add support for ARMv8.5-PMU 64-bit counters
arch/arm64/include/asm/cpufeature.h | 16 ++++++
arch/arm64/include/asm/perf_event.h | 3 +-
arch/arm64/include/asm/sysreg.h | 5 ++
arch/arm64/kernel/perf_event.c | 86 +++++++++++++++++++++++------
arch/arm64/kvm/sys_regs.c | 11 ++++
include/linux/perf/arm_pmu.h | 1 +
6 files changed, 104 insertions(+), 18 deletions(-)
--
2.21.0
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