Improving idle behavior in tickless systems

I'm wondering about systems that contain multiple cooperating CPUs and devices (incl GPUs with DMA
capabilities etc) and whose CPUs may vary in power draw (which I'm presuming will weight the total cost
calculation).

Do the prediction algorithms only consider interrupts to a particular core, independently from equivalent
calculations for another core? What of interrupts due to IPC or other software-initiated interrupts?
What about convoying effects between cores doing different ideas of interdependent userland parallelism?

Seems like an overall optimum might not be achieved without a higher level model of activities (e.g, should
file system drivers consider what their scheduling and consolidations might do to cpuidle calculations?).
And should the programmer be able to hint stuff, like known syncings to, say video refresh, or continuous
DMA input circular buffer segment transitions, e.g., for audio samples at a given sample frequency etc?

Can CPU idle state transitions themselves do hardware interrupts accepted by a designated low power core
doing scheduling work? Open invention gift if not ;-)