Intel Skylake/Kaby Lake processors: broken hyper-threading

Depends what you mean by "similar", and "hundreds" might be an exaggeration if you only count a particular type of bug, though I think it's still slightly worrying to see what a fragile foundation our software is running on (and amazing that in practice it works as well as it does).

ARM seems to avoid publishing errata publicly itself, but e.g. http://www.nxp.com/docs/pcn_attachments/15997_IMX6DQCE.pdf lists about 130 errata for an SoC, including many CPU bugs (Cortex-A9 in this case), of which several sound like they can be triggered by userspace code, including:

"ARM: 743622 - Faulty logic in the Store Buffer may lead to data corruption", triggered by a particular sequence of writes. (Workaround is to disable some Store Buffer optimisation.)

"ARM: 751473 - Under very rare circumstances, Automatic Data prefetcher can lead to deadlock or data corruption". (Workaround is to disable automatic data prefetcher (with minimal effect on performance).)

"ARM: 743623 - Bad interaction between a minimum of seven PLDs and one Non-Cacheable LDM can lead to a deadlock". (Workaround is to not do that, or to globally disable PLD instructions (with significant effect on performance).)

There are also things like https://gcc.gnu.org/ml/gcc-patches/2014-10/msg00906.html (Cortex-A53 multiply-accumulate can give incorrect result) and https://sourceware.org/ml/binutils/2015-03/msg00446.html (Cortex-A53 can get incorrect result from an ADRP instruction near the end of a 4KB page), where the workarounds involve patching the toolchain and rebuilding all the software in the entire world (which is still much cheaper than recalling all the chips).

That's not hundreds, but it seems unsurprising to find several user-triggerable bugs like this in each new CPU. This Intel one seems relatively mild since it can be fixed with a microcode update, no rebuilding or recalling needed.