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Intel Skylake/Kaby Lake processors: broken hyper-threading

Intel Skylake/Kaby Lake processors: broken hyper-threading

Posted Jun 27, 2017 4:36 UTC (Tue) by eru (subscriber, #2753)
In reply to: Intel Skylake/Kaby Lake processors: broken hyper-threading by areilly
Parent article: Intel Skylake/Kaby Lake processors: broken hyper-threading

Would it not be a reasonable translation of char b = i >> 8? (with no other usage of the value i >> 8 nearby).


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Intel Skylake/Kaby Lake processors: broken hyper-threading

Posted Jun 27, 2017 5:11 UTC (Tue) by areilly (guest, #87829) [Link]

Yes, and I've just verified that clang (at least) will generate movb %dh, 0(%rax) in at least one test case. Put it in a loop though and it'll happily vectorise it into shifts and shuffles.

That use doesn't feel like one that would upset a modern (threaded) pipeline though, because there is no chance of a write-after-read style problem. I think that the issue is much more likely to involve writing to one of the [abcd]h registers, which would need to be unpacked into a read-modify-update sequence of micro-ops. For "make an int from left-shifted bytes" style code, I've only seen the compiler generate byte loads followed by left-shifts, rather than loading byte values directly into high reg bytes.

Intel Skylake/Kaby Lake processors: broken hyper-threading

Posted Jun 27, 2017 17:46 UTC (Tue) by pbonzini (subscriber, #60935) [Link]

Yes, but the compiler likely would only generate it at -Os (optimize for size).


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