Tracepoint challenges

Posted Nov 9, 2016 12:59 UTC (Wed) by anton (subscriber, #25547)
Parent article: Tracepoint challenges

The issue seems to be similar to that of performance monitoring events in CPUs: While CPU architects are very reluctant at changing existing architectural features, because they don't want to break programs, they have shown little restraint in changing the performance monitoring event interfaces, and which events one can monitor. In particular, the events for specific microarchitectural features come and go as the microarchitecture changes. However, because, e.g., instructions, branch instructions, and memory accesses are architectural features, there have always been events for that. Events for common microarchitectural features like branch prediction and cache hits/misses have also been common.