xen: information disclosure
| Package(s): | xen | CVE #(s): | CVE-2016-3158 CVE-2016-3159 | ||||||||||||||||||||||||||||||||||||||||||||||||
| Created: | April 11, 2016 | Updated: | April 13, 2016 | ||||||||||||||||||||||||||||||||||||||||||||||||
| Description: | From the Red Hat bugzilla:
There is a workaround in Xen to deal with the fact that AMD CPUs don't load the x86 registers FIP (and possibly FCS), FDP (and possibly FDS), and FOP from memory (via XRSTOR or FXRSTOR) when there is no pending unmasked exception. However, this workaround does not cover all possible input cases. This is because writes to the hardware FSW.ES bit, which the current workaround is based on, are ignored; instead, the CPU calculates FSW.ES from the pending exception and exception mask bits. Xen therefore needs to do the same. Note that part of said workaround was the subject of XSA-52. A malicious domain may be able to leverage this to obtain sensitive information such as cryptographic keys from another domain. | ||||||||||||||||||||||||||||||||||||||||||||||||||
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