TLB cache misses

One of the improvements in DPDK was to keep the packet buffer in a large page. The usual page table on x86 has 4K pages, and as packet buffers are large (at best 2 packets per page for receive), processing packets uses many page tables entries (PTE), as well as wiping the TLB. Keeping the packets in a hugepage reduces the number of TLB entries required, and the associated possibility of a TLB miss, and the possibility that the page lookup has to be retrieved from RAM. Looking at TLB hit ratios is another important optimization tool.