How much context do we need per ring?
Enough to distinguish access from ring-0 to the access from ring-3, heh. Either you add tags to all the commands and all the data in the pipelines or you flush the pipeline after flush.
Basically the question is: if "mov [some_address], register" should succeed in ring-0 and fail in ring-3 then how do you detect this? Either you keep this metainformation near the information itself (that is: when you assign registers you now have 2-3-4x more physical registers and thus more complex logic to assign them) or you need to flush the pipeline after ring switch. First approach will mean larger core pieces (and thus slower CPU frequency), second approach will mean slow ring switch.
According to Wikipedia, ring switches can be relatively fast, presumably because they don't need to reload the page table.
The key word here is "relatively". If you flush the pipeline then there are 15-20 ticks stall and in that time CPU can execute about 30-40 simple commands.
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