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Betrayed by a bitfield

Betrayed by a bitfield

Posted Feb 7, 2012 17:06 UTC (Tue) by BenHutchings (subscriber, #37955)
In reply to: Betrayed by a bitfield by daglwn
Parent article: Betrayed by a bitfield

Insane? I imagine the 6- and 16-bit processor guys said the same when Alpha appeared.

Yes, Alpha's lack of 8- and 16-bit store instructions was insane. That's why they were added in later versions of the architecture.


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Betrayed by a bitfield

Posted Feb 8, 2012 0:11 UTC (Wed) by daglwn (guest, #65432) [Link]

There are plenty of architectures that have these kinds of restricted loads and stores. The old Cray machines only ever operated on 64 bit words, for example.

And often a machine implements the smaller accesses but there is a performance penalty due to alignment issues and the bus/DRAM access architecture. It's not uncommon for the RMW to be faster.

Betrayed by a bitfield

Posted Feb 8, 2012 13:57 UTC (Wed) by nix (subscriber, #2304) [Link]

SPARC is another major example of an arch with alignment-restricted loads and stores. I have dim memories that suggest that MIPS might be as well.

It's actually easier to come up with a list of architectures that do *not* require natural alignment on loads and stores than to come up with a list of those that do.


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