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Sharing buffers between devices

Sharing buffers between devices

Posted Aug 18, 2011 19:58 UTC (Thu) by dougg (guest, #1894)
Parent article: Sharing buffers between devices

A more efficient dd between storage devices could be implemented if the data did not need to be shunted in and out of the user space.


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Sharing buffers between devices

Posted Aug 19, 2011 11:40 UTC (Fri) by epa (subscriber, #39769) [Link]

I remember being told about IBM's Micro Channel architecture (MCA) and its ability to let devices talk directly to each other across the MCA bus, without involving the CPU. I imagine this was never really used in PC-compatible systems although it might have been in certain MCA-based mainframes or RS/6000 systems. There might also be the chance for two disks attached to the same controller to copy data directly between themselves without going through the host system at all.

Sharing buffers between devices

Posted Aug 19, 2011 20:31 UTC (Fri) by giraffedata (subscriber, #1954) [Link]

A more efficient dd between storage devices could be implemented if the data did not need to be shunted in and out of the user space.

The shunting in and out of user space is easy to eliminate: mmap.

That leaves you with the copying from one device's buffer to the other. For that, Linus invented the 'splice' system call about ten years ago and, as justincormack points out in another comment on this article, actually implemented in 2005. Splice takes two file descriptors and a length as arguments and reads that many bytes from one of the devices and writes it to the other, by DMAing into, then out of, the same memory. https://lwn.net/Articles/119682/ . I don't know what the current state of deployment is, though.

The MCA thing would presumably be the next step, where the data doesn't have to stop over in system memory.

In big systems, where the storage devices are rather separate from the CPUs, this exists in the form that you can tell a device to send some of its contents directly to another device, e.g. through a fibre channel network. I guess the same thing over a PCI-class network can't be far behind.

In fact, my guess is that the bus protocol itself allows this in PCI Express and Infiniband; I don't think the CPU/main memory is particularly special in those protocols. Does somebody know?


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