Little-endian PowerPC [LWN.net]

Little-endian PowerPC

Posted Oct 7, 2010 14:21 UTC (Thu) by etienne (guest, #25256)
In reply to: Little-endian PowerPC by jengelh
Parent article: Little-endian PowerPC

Last time I looked gcc was not able to generate (did not know about) the bswap instruction.
I do not think gcc knows about "load/store word with byte reversed" of PPC neither.
For BE CPU, you still need some assembly instuctions to cast the value 3 in a 16 bits word to the value 3 in a byte, and pass its address... at least in gcc you need an explicit temporary.
It is easy to assume (source of a lot of bugs) that when an constant integer contains the value 15 you can cast the address of that integer to a char or short pointer; to get rid of those bugs it seems people prefer little endian.
But basically your byte endianess is directly depending on the endianess of all the environment, not only the network interface.
The "best" I worked with was a big endian main processor connected to a little endian coprocessor connected to a big endian FPGA: at the time you know that the message in the coprocessor contains a 32 bits value and you should byte-swap it, you should byte-swap it back to write it to the FPGA... Basically do not byte-swap it at all but for display/debug.

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Little-endian PowerPC

Posted Oct 7, 2010 14:47 UTC (Thu) by jengelh (subscriber, #33263) [Link] (1 responses)

>Last time I looked gcc was not able to generate (did not know about) the bswap instruction.

Perhaps you need to update from that ancient gcc version ;-)

int main(int argc, char **argv) { printf("%d\n", htonl(argc)); return 0; } compiled with gcc-4.5 -O3 -static on x86_64 gives me a bswap in objdump. bswap has been there since 80486.

>some assembly instuctions to cast the value 3 in a 16 bits word to the value 3 in a byte,

Well, wouldn't that be just AND r0, 0xFF.

Little-endian PowerPC

Posted Oct 7, 2010 15:38 UTC (Thu) by etienne (guest, #25256) [Link]

> Perhaps you need to update from that ancient gcc version ;-)

Still no GCC-4.5 here and on ia32, if your example no more calls the function "htonl" (which for GCC-4.4.5 is a library function written manually in assembler - I just checked the whole calling sequence by objdump), that is a very welcome improvement!

> Well, wouldn't that be just AND r0, 0xFF.

Unfortunately a register do not have an address to pass to a function, so you need to allocate some temporary space on the stack and copy your register there...

Little-endian PowerPC

Posted Oct 7, 2010 18:55 UTC (Thu) by daniel (guest, #3181) [Link] (2 responses)

<i>Last time I looked gcc was not able to generate (did not know about) the bswap instruction.</i>

I doubt that, however what GCC does need is support for endian variable attributes with appropriate code generation. Last I looked, GCC has no such feature.

Little-endian PowerPC

Posted Oct 8, 2010 14:25 UTC (Fri) by etienne (guest, #25256) [Link] (1 responses)

> I doubt that

GCC do know about the bswap instruction since 4.0 (I just checked the source), but I did not find a way to make GCC use it (i.e. either inline the bswap() or recognise the three shift sequence) on a i386 host...

Little-endian PowerPC

Posted Oct 8, 2010 15:29 UTC (Fri) by jengelh (subscriber, #33263) [Link]

>but I did not find a way to make GCC use it (i.e. either inline the bswap() or recognise the three shift sequence) on a i386 host...

Works here. Optimizer starts recognizing int s = ((((argc) & 0xff000000) >> 24) | (((argc) & 0x00ff0000) >> 8) | (((argc) & 0x0000ff00) << 8) | (((argc) & 0x000000ff) << 24)); on -O2 and issues a bswap for it.

Alternatively, you could use the same trick as glibc's htonl: int s = __bswap_32(argc). Or even directly __builtin_bswap32 as documented in gcc.info.