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What's new in GCC 4.5?

What's new in GCC 4.5?

Posted May 13, 2010 0:26 UTC (Thu) by creemj (subscriber, #56061)
In reply to: What's new in GCC 4.5? by foom
Parent article: What's new in GCC 4.5?

I take it from this discussion that the Intel processors do not have a CPU/FPU instruction to convert the 80 bit representation to 64bit IEEE compliant representation (and vice versa) directly within the FPU register without a memory store? To myself, who knows very little of Intel architecture, that is surprising.

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What's new in GCC 4.5?

Posted May 13, 2010 10:09 UTC (Thu) by mpr22 (subscriber, #60784) [Link]

x86 is fundamentally a big bag of hacks and kludges. Glaring deficiencies are never surprising.

What's new in GCC 4.5?

Posted May 17, 2010 6:19 UTC (Mon) by cph (guest, #1433) [Link]

On the other hand, the programmer can always set the floating-point control word to do 53-bit precision; this makes the in-register values have the same precision as the in-memory ones.

I don't understand why the article didn't mention this. It's a simple fix that gives consistent results regardless of the memory/register optimization.

What's new in GCC 4.5?

Posted May 18, 2010 21:31 UTC (Tue) by dark (guest, #8483) [Link]

This doesn't sound like a complete solution. I think you would also have to use 'double' everywhere and excise 'float' from all your code in order to get consistent results. Though it's probably still okay to use 'float' in arrays as long as you convert to 'double' for all calculations.

What's new in GCC 4.5?

Posted May 13, 2010 15:52 UTC (Thu) by foom (subscriber, #14868) [Link]

You're not really supposed to use the x87 FPU these days, anyways. Use SSE2 instead, which actually uses 64bit FP operations instead of 80bit. Then you don't have the problem in the first place.

Unfortunately most software for Linux/x86 is compiled without SSE2 enabled, because distros want to support pre-Pentium4 processors.

What's new in GCC 4.5?

Posted May 15, 2010 6:02 UTC (Sat) by RCL (subscriber, #63264) [Link]

Just use 64-bit OS. Luckily, there's no FPU in x86-64, it's gone together with MMX.

What's new in GCC 4.5?

Posted May 22, 2010 14:00 UTC (Sat) by robert_s (subscriber, #42402) [Link]

That's not true.

They're still there, but there are just better replacements for both of them. The only situation where this might be true is if bit 29 of CPUID 0x80000001 is not set, in which case you can't use MMX in long mode.

x87 is always there.

What's new in GCC 4.5?

Posted May 21, 2010 14:10 UTC (Fri) by foo-bar (guest, #22971) [Link]

On 32-bit x86 SSE2 is sometimes slower than x87.

What's new in GCC 4.5?

Posted May 18, 2010 16:47 UTC (Tue) by pharm (guest, #22305) [Link]

No, Intel processors can switch between 64-bit & 80-bit floating point register mode. You can use the -mpc option to gcc to force 64-bit floats.

Why people bang on about -ffloat-store instead of pointing people to -mpc64 if they want to truncate floats to 64 bits on Intel platforms I'm not sure.

Check out the FLDCW (Floating Point Load Control Word) instruction for the gory details.

What's new in GCC 4.5?

Posted May 18, 2010 16:50 UTC (Tue) by pharm (guest, #22305) [Link]

Oh wait, I see what you're saying.

I suppose you can set the control word to 53-bit mantissa & copy a value from one FP register to another. That would be a bit slow though.

What's new in GCC 4.5?

Posted May 31, 2010 15:52 UTC (Mon) by Spudd86 (guest, #51683) [Link]

Err doesn't setting the control word before doing ANYTHING mean that you'll keep a 53 bit mantissa throughout?

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