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Memory management for virtualization

Memory management for virtualization

Posted Apr 8, 2010 18:49 UTC (Thu) by anton (subscriber, #25547)
Parent article: Memory management for virtualization

My guess is that the "better CPU" features that Linus refers to is stuff like the AMD K10's nested paging ("Rapid Virtualization Indexing"), and maybe also having a large enough (L2) TLB (although the latter does not just help virtualization).

Larger pages are also helpful for non-virtualized applications that perform lots of memory accesses with low spatial locality with a large-enough footprint. An extreme case would be walking through memory with a 4160 byte stride: Every step would consume a TLB entry and a cache line entry; Once you have run out of TLB entries (on AMD K10: 48 L1 TLB entries, 512 L2 TLB entries, 1024 L1 cache lines, 8192 L2 cache lines), you can start over, and you will have a workload that hits the cache and misses the TLB all the time.


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Memory management for virtualization

Posted Apr 8, 2010 21:31 UTC (Thu) by avik (guest, #704) [Link]

Nested paging actually makes things worse: the cache footprint of the page table doubles, and a tlb fill needs 24 memory accesses instead of 4. Large pages are a way to reduce the cache footprint and tlb fill cost to something tolerable.

Memory management for virtualization

Posted Apr 9, 2010 10:36 UTC (Fri) by anton (subscriber, #25547) [Link]

Nested paging makes things worse than what? If it's worse than whatever they do in virtualization without them, why were they introduced?

Memory management for virtualization

Posted Apr 9, 2010 10:43 UTC (Fri) by avik (guest, #704) [Link]

Nested paging has worse cache footprint and tlb fill latency than shadow paging. However shadow paging is a lot worse in terms of scalability and mmu operation costs, so nested paging is an overall win (by a large margin).

So, nested paging is overall much better than shadow paging (but worse in some aspects), large pages bridge the gap and make nested paging better overall.


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