Actually, since Intel processors use an inclusive cache, the original statement is correct. If it isnt in L1, it isnt in L2, either, since L2 includes all the contents of L1.
L2 contains everything in L1, but, since it's larger, it contains data which is not in L1 as well. If L2 cannot satisfy an occasional L1 cache miss, why does it exist? I have a question into Ulrich on how he really wanted this paragraph to read, stay tuned.
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