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Memory part 6: More things programmers can do

Memory part 6: More things programmers can do

Posted Oct 31, 2007 19:11 UTC (Wed) by phip (guest, #1715)
Parent article: Memory part 6: More things programmers can do

Figure 6.11 shows the equivalent measurements when running the code on a single processor, quad core machine (Intel Core 2 QX 6700). Even with this processor's two separate L2s the test case does not show any scalability issues. There is a slight overhead when using the same cache line more than once but it does not increase with the number of cores. {I cannot explain the lower number when all four cores are used but it is reproducible.}

Intel's Core 2 QX 6700 and QX 6800 quad core chips, for instance, have two separate L2 caches.

If I understand correctly, cores 0 and 1 share an L2, and cores 2 and 3 share a second L2.

With 4 cores, core 2 and core 3 will effectively prefetch lines into the shared L2 for each other. With only 3 cores, core 2 has to pay the full penalty for all its L2 cache misses.

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Memory part 6: More things programmers can do

Posted Nov 1, 2007 17:22 UTC (Thu) by ajross (guest, #4563) [Link]

Yes.  The quad core chips are basically two dual core CPUs with some SMP glue logic and a
unified memory controller.

Intel Quad-core implementation

Posted Nov 9, 2007 11:00 UTC (Fri) by anton (subscriber, #25547) [Link]

The current Intel quad core packages are two dual-core chips in a multi-chip module (MCM), connected to a common bus. There is no glue logic (SMP logic is on each of the chips), and the memory controller is in a different package (the MCH).

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