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Memory part 2: CPU caches

Memory part 2: CPU caches

Posted Oct 31, 2007 17:11 UTC (Wed) by mas4042 (guest, #48162)
Parent article: Memory part 2: CPU caches

Fig 3.26 doesn't make any sense to me.

I'm supposed to believe that the Core2 can sustain 16B/cycle read bandwidth out to a working
set of 512M?

Lets assume it was a 2 GHz part to make the math easy.  To sustain 16B/clock would require 32
GB/sec bandwidth to main memory.

What am I missing?

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