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Memory part 4: NUMA support

Memory part 4: NUMA support

Posted Oct 22, 2007 0:35 UTC (Mon) by dlang (subscriber, #313)
Parent article: Memory part 4: NUMA support

several comments

a radius 1 arrangement can actually include 3 CPUs, think a triangle, every machine is at most
one hop from the memory

the Opteron already has versions that have four HT links, they are the 800/8000 series chips
targeted at 8 cpu systems


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Memory part 4: NUMA support

Posted Oct 25, 2007 12:47 UTC (Thu) by joib (subscriber, #8541) [Link]

the Opteron already has versions that have four HT links, they are the 800/8000 series chips targeted at 8 cpu systems

That is not correct. All current Opterons (including the 800(0) series) have 3 HT links. The difference is that in the 800(0) series all 3 HT links are cache coherent, whereas there is only one cache coherent link on the 200(0) series and none on the 100(0) series (and athlon64).

That being said, the recently released quad core Opterons do in principle support 4 HT links, but so far they are using the existing socket so they are limited to 3 links until the next generation socket is introduced.

Memory part 4: NUMA support

Posted Oct 27, 2007 6:51 UTC (Sat) by dlang (subscriber, #313) [Link]

it's also possible to have a radius-3 arrangement with only 3 links
1--2--
|  | |
3--4 |
|  | |
5--6 |
|  | |
7--8--

this leaves CPU's 1 and 7 with an extra link available for connections to a southbridge.

Memory part 4: NUMA support

Posted Jan 10, 2008 14:27 UTC (Thu) by rengolin (subscriber, #48414) [Link]

> a radius 1 arrangement can actually include 3 CPUs, think a triangle, every machine is at
most one hop from the memory

Actually it's N+1 being N the number of dimensions you build your computer. 

In the three-dimensional reality a tetrahedron (4CPUs) is radius 1, in the two-dimensional a
triangle and so on, therefore we can increase the number of CPUs in radius 1 by building
computers in higher dimensions! ;)


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