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The story repeats itself

The story repeats itself

Posted Sep 19, 2007 17:00 UTC (Wed) by khim (subscriber, #9252)
In reply to: Large pages, large blocks, and large problems by james
Parent article: Large pages, large blocks, and large problems

Deja vu: the same thing happened when question about more the 4GB of memory in 32-bit system was raised. Of course it's insane to try to handle 16GiB or 32GiB with 32bit CPU. Of course the proper solution is switch to 64bit CPU. But when the most popular arch is 32-bit and users need huge memory systems - what can you do ?

Here we have the same situation. Most CPUs are balanced (PPC, Athlon64, etc), but there are one vendor which sells two architectures of CPU which are seriously unbalanced. Can we safely ignore this obscure vendor and these crippled CPUs ? Not when vendor is called Intel and CPUs are Pentium 4 and Core 2. They both only have 128-items TLB (enough for 512KiB with 4KiB pages) and 4MiB of cache (at least in some models). That's 8 times difference! Yes, this is insane, yes, this is problem of CPU design. Yet when it's the most popular vendor and the "crippled architecture" is the most popular CPU from said vendor - you can not just ignore the problem and hope that it'll go away.

There are rumors that Vista SP1 will use 4MB pages to speedup I/O...

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The story repeats itself

Posted Sep 19, 2007 17:23 UTC (Wed) by proski (subscriber, #104) [Link]

Isn't Core 2 64-bit? That problem is going away. And 16 Gb of RAM costs significantly more than a CPU and a motherboard that can support it properly, and it has always been like that.

The same applies to the cache. Changing the CPU will cost fraction of the memory it's supposed to support.

The story repeats itself

Posted Sep 19, 2007 17:38 UTC (Wed) by khim (subscriber, #9252) [Link]

Core 2 is 64bit only, but people needed 16GiB of RAM years ago when x86-compatible 64bit CPUs were just a project. Thus PAE support was added to Linux.

The same - with TLB today: may be someday we'll have the truly balanced architecture but today - we don't. Add it's not clear if we'll have balanced architecture tomorrow: TLB must be fast (or else it's useless) but it's hard to create large and fast cache. Of course it's possible to use 2-level TLB (like AMD does today), but it's not some minor modification - it's possible that we'll be forced to wait few years till the new Intel's design. And all these years Linux will be worse then Windows... not a good position...

The story repeats itself

Posted Sep 19, 2007 22:44 UTC (Wed) by proski (subscriber, #104) [Link]

I don't see any references to Windows in the story.

The story repeats itself

Posted Sep 20, 2007 0:52 UTC (Thu) by sayler (guest, #3164) [Link]

"Core 2 is 64bit only"



Posted Sep 20, 2007 21:09 UTC (Thu) by khim (subscriber, #9252) [Link]

Perils of editing. Initially I wanted so say that only "Core 2" is 64bit while Pentium 4 (except latest models of Prescott), Pentium 3 and so on are 32bit. Phrase was too cumbersome and I've removed everything but the "only" word was left after editing...

The story repeats itself

Posted Sep 27, 2007 13:31 UTC (Thu) by anton (subscriber, #25547) [Link]

[...] Pentium 4 and Core 2. They both only have 128-items TLB (enough for 512KiB with 4KiB pages)
Note that this assumes that each page is fully utilized with hot data, i.e., the best case. That's rarely the case and that's why cache lines are smaller than a page. So, in the worst case, 128 TLB entries cover only 128 cache lines, i.e., with 64-byte L1 cache lines, 8KB. I have no data on typical cases, but if half the page contains hot data, a 128-entry TLB will cover only 256KB of data in the caches. You can then hope that your working set is smaller, or you will see TLB thrashing.

If page utilization is a problem, larger pages will probably have limited benefit: the relative utilization (hot data/page size) will probably go down. However, as long as the absolute utilization (hot data/page) goes up, larger pages will still be useful in terms of reducing TLB misses; they do have other costs, though.

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