IIRC, the initial dual-cores from AMD and Intel will not share any cache.
Intel's (initial) implementation in particular is basically two
independent CPUs on the same die. Even when shared L2 caches are
implemented, it seems that sharing an L2 cache will provide lower
bandwidth to this kind of exploit, which benefits hugely from the shared
L1 cache of the two hyperthreads.
Note that IBM's POWER4 shares caches across multiple cores and the POWER5
also has SMT...
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