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Is hyperthreading dangerous?

Is hyperthreading dangerous?

Posted May 19, 2005 9:42 UTC (Thu) by filipjoelsson (guest, #2622)
Parent article: Is hyperthreading dangerous?

Does this very theoretical exploit affect multicore systems too? I'm not sure I have this right, but I think they sharing cache too. Or is the (still very theorietical) exploit dependent on the feature that the hostile thread and the cryptographic one do not run at the same time?

In any case, I have the answer:
<TIC>This is the perfect exploit to close with security thorugh obscurity. We have to lessen the risque that the two processes happen to be in the same processor cache at the same time. This is best (depending on wether you share my definition of 'best') done by getting an 8-way SMP system, preferably dualcore. (Well, at least _I_ would prefer that, wouldn't you?) Thus the chance would be slim, at best, that the two processes would schedule to the same processor at the same time. (Now, all I need is to persuade my wife that this is necessary in the name of security.)</TIC>

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Is hyperthreading dangerous?

Posted May 19, 2005 15:13 UTC (Thu) by khim (subscriber, #9252) [Link]

Does this very theoretical exploit affect multicore systems too?

Yes and no. Yes - it's possible to use the same technique for dual-core systems. But in reality it'll require way too much brute force. The problem with Hyper-Threading is size of L1 cache - it's too small. Multicore systems only share L2 cache (if even that) and it's much bigger so problem becomes pure theory.

Dual cores...

Posted May 26, 2005 13:30 UTC (Thu) by MarkWilliamson (guest, #30166) [Link]

IIRC, the initial dual-cores from AMD and Intel will not share any cache.
Intel's (initial) implementation in particular is basically two
independent CPUs on the same die. Even when shared L2 caches are
implemented, it seems that sharing an L2 cache will provide lower
bandwidth to this kind of exploit, which benefits hugely from the shared
L1 cache of the two hyperthreads.

Note that IBM's POWER4 shares caches across multiple cores and the POWER5
also has SMT...

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