cxgb4: Add Chelsio T7 support

This patch series introduces base support for the next-generation Chelsio
T7 adapter family into the cxgb4 driver. 

T7 follows the previous T6 architecture, bringing significant performance
upgrades to the platform. The new chip comes in single, dual, and 4-port
variants, introducing capabilities for hardware link speeds up to
400Gbps alongside native PCIe Gen5 bus support.

To accommodate the expanded features, multi-core architecture.
This series refactors core driver subsystems while preserving backward 
compatibility for legacy hardware:

1. Foundational registers, chip identification tokens, and hardware
   constants are introduced to handle expanded microprocessor tracking,
   larger SGE contexts, and flexible flash memory configurations.
2. CPL structures and firmware command layouts are upgraded to support the
   wider traffic processor filter tuples and high-speed link profiles.
3. The driver's modular design is improved by moving bus-specific setup
   routines out of cxgb4_main.c into a dedicated cxgb4_pci module.
4. The core hardware abstraction layer, SGE processing pipelines,
   filtering engine, and ethtool management layouts are extended to
   correctly target T7 interfaces and configuration profiles.
5. The cudbg library and debugfs diagnostic components are refactored
   to output versioned structural dumps, ensuring user-space tools can
   seamlessly process T7 operational telemetry.

This series has been tested for compilation and NIC traffic on T7 Chip.
Please review.

Potnuri Bharat Teja (6):
  cxgb4: Add T7 register definitions and core structures
  cxgb4: Add T7 chip type identification and HW constants
  cxgb4: Add T7 CPL messages, FW constants, and PCI IDs
  cxgb4: Add versioned structures and scratch buffs
  cxgb4: Add T7 indirect regs and update library
  cxgb4: Move PCI initialization logic to cxgb4_pci.c

 drivers/net/ethernet/chelsio/cxgb4/Makefile   |    2 +-
 .../net/ethernet/chelsio/cxgb4/cudbg_common.c |   30 +
 .../net/ethernet/chelsio/cxgb4/cudbg_entity.h |  147 ++-
 drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h |   54 +-
 .../ethernet/chelsio/cxgb4/cudbg_indir_reg.h  |   43 +
 .../chelsio/cxgb4/cudbg_indir_reg_t7.h        | 1113 +++++++++++++++++
 .../net/ethernet/chelsio/cxgb4/cudbg_lib.c    |  902 +++++++++++--
 .../net/ethernet/chelsio/cxgb4/cudbg_lib.h    |   50 +-
 .../ethernet/chelsio/cxgb4/cudbg_lib_common.h |    4 +
 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h    |  194 ++-
 .../net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c  |   16 +
 .../net/ethernet/chelsio/cxgb4/cxgb4_pci.c    |  370 ++++++
 .../net/ethernet/chelsio/cxgb4/cxgb4_pci.h    |   36 +
 .../net/ethernet/chelsio/cxgb4/t4_chip_type.h |   10 +
 drivers/net/ethernet/chelsio/cxgb4/t4_hw.h    |  136 +-
 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h   |  109 +-
 .../ethernet/chelsio/cxgb4/t4_pci_id_tbl.h    |   21 +
 drivers/net/ethernet/chelsio/cxgb4/t4_regs.h  |  478 ++++++-
 drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h   |   16 +
 .../net/ethernet/chelsio/cxgb4/t4_values.h    |   15 +-
 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h |   82 +-
 .../net/ethernet/chelsio/cxgb4/t4fw_version.h |    9 +
 22 files changed, 3609 insertions(+), 228 deletions(-)
 create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h
 create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h
 create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c
 create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h

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2.39.1