| From: |
| Chaoyi Chen <kernel-AT-airkyi.com> |
| To: |
| Sandy Huang <hjc-AT-rock-chips.com>, Heiko Stübner <heiko-AT-sntech.de>, Andy Yan <andy.yan-AT-rock-chips.com>, Maarten Lankhorst <maarten.lankhorst-AT-linux.intel.com>, Maxime Ripard <mripard-AT-kernel.org>, Thomas Zimmermann <tzimmermann-AT-suse.de>, David Airlie <airlied-AT-gmail.com>, Simona Vetter <simona-AT-ffwll.ch>, Guochun Huang <hero.huang-AT-rock-chips.com> |
| Subject: |
| [PATCH v2 0/3] DSI Controller improvements for Rockchip platforms |
| Date: |
| Wed, 03 Jun 2026 11:35:29 +0800 |
| Message-ID: |
| <20260603033532.164-1-kernel@airkyi.com> |
| Cc: |
| dri-devel-AT-lists.freedesktop.org, linux-arm-kernel-AT-lists.infradead.org, linux-rockchip-AT-lists.infradead.org, linux-kernel-AT-vger.kernel.org, Chaoyi Chen <chaoyi.chen-AT-rock-chips.com> |
| Archive-link: |
| Article |
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
This series is dedicated to enhancing the DSI controller and PHY timing
interaction, refining the lane rate calculation, and addressing the
associated hardware limitations.
Changes in v2:
- Link to v1: https://lore.kernel.org/all/20260324085838.90-1-kernel@ai...
- Fix the unit conversion for max_mbps.
- Split the lane rate calculation into a separate patch.
- Add more comment about timing config.
Chaoyi Chen (3):
drm/rockchip: dsi: Add maximum per lane bit rate calculation
drm/rockchip: dsi: Add dphy_get_timing support for multiple PHY types
drm/rockchip: dsi: Relax the lane rate margin requirements
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 66 +++++++++++++++++--
1 file changed, 60 insertions(+), 6 deletions(-)
--
2.53.0
