| From: |
| "lianfeng.ouyang" <lianfeng.ouyang-AT-starfivetech.com> |
| To: |
| Andi Shyti <andi.shyti-AT-kernel.org>, Rob Herring <robh-AT-kernel.org>, Krzysztof Kozlowski <krzk+dt-AT-kernel.org>, Conor Dooley <conor+dt-AT-kernel.org>, Mika Westerberg <mika.westerberg-AT-linux.intel.com>, Andy Shevchenko <andriy.shevchenko-AT-linux.intel.com>, Jan Dabros <jsd-AT-semihalf.com> |
| Subject: |
| [PATCH v1 0/3] i2c: dwc: Add I2C DWC master/slave support for StarFive JHB100 |
| Date: |
| Thu, 21 May 2026 11:43:37 +0800 |
| Message-ID: |
| <20260521034340.27837-1-lianfeng.ouyang@starfivetech.com> |
| Cc: |
| linux-i2c-AT-vger.kernel.org, devicetree-AT-vger.kernel.org, linux-kernel-AT-vger.kernel.org, Lianfeng Ouyang <lianfeng.ouyang-AT-starfivetech.com> |
| Archive-link: |
| Article |
From: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
The Synopsys DesignWare Core (DWC) I2C controller is a variant of the
widely-used DesignWare I2C IP, with a distinct register layout and
enhanced features such as SMBus Alert and programmable FIFO depths.
This patch series introduces support for this controller as implemented
on the StarFive JHB100 platform, which utilizes it for both master and
slave operations (e.g., for MCTP over I2C).
The series is structured as follows:
1. Adds the device tree binding document for the snps,dwc-i2c compatible.
2. Prepares the existing i2c-designware-core by exporting and making
certain key functions overridable, allowing code reuse.
3. Introduces the new i2c-dwc-core driver, with separate modules for
master and slave functionality, based on the 2023-07 revision of the
Synopsys IP manual.
Key differences from the Existing i2c-designware Driver
1. The DWC IP's offsets for all key registers are redefined. The driver
maps to the correct addresses by overriding macros from the core
header file in a new header (i2c-dwc-core.h).
2. The host and slave of DWC IP need to perform probe callbacks
separately, so they cannot be directly set through i2c_dew_set_mode
3. Interrupts are cleared by writing​ to the corresponding bits in the
INTR_CLRregister (write-1-to-clear).
4. The DWC controller's IC_ENABLEregister contains an additional
TX_CMD_BLOCKcontrol bit. When enabling the controller, the driver must
ensure this bit is cleared. When disabling, only the ENABLEbit is
cleared, preserving other configurations.
Lianfeng Ouyang (3):
dt-bindings: i2c: snps,dwc-i2c: Add StarFive JHB100 bindings
i2c: designware: Export symbols and add __weak for DWC I2C driver
i2c: dwc: Add StarFive JHB100 I2C master/slave support
.../devicetree/bindings/i2c/snps,dwc-i2c.yaml | 120 +++++
MAINTAINERS | 7 +
drivers/i2c/busses/Kconfig | 34 ++
drivers/i2c/busses/Makefile | 3 +
drivers/i2c/busses/i2c-designware-common.c | 57 ++-
drivers/i2c/busses/i2c-designware-core.h | 25 +
drivers/i2c/busses/i2c-designware-master.c | 14 +-
drivers/i2c/busses/i2c-designware-platdrv.c | 6 +
drivers/i2c/busses/i2c-designware-slave.c | 4 +-
drivers/i2c/busses/i2c-dwc-core.h | 192 ++++++++
drivers/i2c/busses/i2c-dwc-master.c | 441 ++++++++++++++++++
drivers/i2c/busses/i2c-dwc-slave.c | 180 +++++++
12 files changed, 1068 insertions(+), 15 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/snps,dwc-i2c.yaml
create mode 100644 drivers/i2c/busses/i2c-dwc-core.h
create mode 100644 drivers/i2c/busses/i2c-dwc-master.c
create mode 100644 drivers/i2c/busses/i2c-dwc-slave.c
--
2.43.0
