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Tier-aware memory-controller limits

By Jonathan Corbet
May 25, 2026

LSFMM+BPF
Joshua Hahn began his session in the memory-management track of the 2026 Linux Storage, Filesystem, Memory Management, and BPF Summit by saying that the memory controller for control groups is intended to provide resource allocation, accounting, and protection from interference by other tasks. But it was not really designed for tiered-memory systems; he is looking for a way to improve that situation.

[Joshua Hahn] Tiered-memory systems have two or more classes of memory, each of which has different performance characteristics. The system's RAM is relatively fast, but also relatively scarce, while plentiful memory on a CXL device may be slower. The memory controller, though, has no awareness of these differences, with the result that two control groups running the same workload under the same policies may perform differently. Without control over the physical placement of memory, the memory controller is not able to provide a consistent execution environment.

Hahn asked, rhetorically, whether anybody cares about this problem. There are, naturally, a number of situations where people do care. Latency-sensitive workloads will suffer if they are relegated to slower memory. Hosting services want to provide fairness across all of their tenants. And, in general, performance should be predictable. It is not possible, for example, to measure performance gains from other work if the execution time of the workload is inherently variable.

The proposed solution is to add a new memory-controller knob, memory_tiered_limits, that would enable tier awareness. Another set of knobs, memory.toptier_min, memory.toptier_low, memory.toptier_high and memory.toptier_max, would regulate how much memory the group is entitled to in the top memory tier, and the maximum amount that it can use. When, for example, usage reaches the memory.toptier_high value, reclaim on that tier would be triggered for that control group.

This scheme, he said, yields more consistent results on tiered-memory systems for a variety of workloads. It can also improve throughput overall; distributing a workload properly across tiers can maximize the use of the available memory bandwidth for all of those tiers.

There are some questions still to be answered, he said. Should reclaim always be triggered when top-tier usage hits the watermark, or should it only happen when there is memory pressure? He suggested that, if there is still top-level RAM available in the system, it might not make sense to limit its use. On the user-interface side, there is the question of how much tuning of tier ratios the user should be allowed to do. Promotion of folios from slower to faster tiers is a longstanding problem with the tiered-memory concept, due to the difficulty of efficiently determining which folios are the right ones to promote. It is a problem here too; Hahn would like to find an efficient solution at the control-group level.

A member of the audience asked whether it was possible to expand this mechanism to more than two tiers. He expressed concern that the toptier name could not be changed, leading to problems where the top tier is some sort of scarce, high-bandwidth memory rather than regular system RAM. Hahn said that he would like to see such a system before trying to adapt the memory controller to it.

Another participant asked about fallback. Within the kernel, if an attempt to allocate top-tier memory fails, the allocator will fall back to slower memory. With this proposal, instead, the controller would trigger reclaim on the control group if the top-tier limit has been reached. Hahn agreed that this is a change in behavior, but said that is a result of introducing a new concept — tiered memory — to the memory controller.

The session wound down with an unfocused discussion on the difficulties of tracking memory used by the networking subsystem in general.

Index entries for this article
KernelMemory management/Control groups
KernelMemory management/Tiered-memory systems
ConferenceStorage, Filesystem, Memory-Management and BPF Summit/2026


to post comments

tier support exist already in a fashion

Posted May 27, 2026 21:09 UTC (Wed) by clameter (subscriber, #17005) [Link] (2 responses)

NUMA nodes are something like tiers and the issues related to reclaim have been an issue there as well. A NUMA node can be specified to have a longer latency than all the other memory nodes, have higher latency and no processors attached.

The system will then preferentially place memory close to the executing threads and only use the slower NUMA node (you may call it a second tier) if memory gets low.

The tradeoff between local reclaim and going off node can be controlled with the "node_reclaim" setting in sysfs.

Linux system with such configurations were common in high performance computers between 2002-2008. The main manufacturer was Hewlett Packard.

tier support exist already in a fashion

Posted May 29, 2026 15:19 UTC (Fri) by paulj (subscriber, #341) [Link] (1 responses)

I was also wondering how this "tiering" was not covered by NUMA.

Another possible issue is that the perception of tiering may *not* be globally uniform. It may be local. E.g., a fast "high tier" memory could be slower than a lower-tier memory IF the "high tier" memory just happens to be located past some number of hops of interconnect. It all depends on how large or small the differences in speed of the different tiers of memory could be, relative to the kinds of interconnects.

A graph potentially may be a better abstraction than a hierarchy, unless it's fairly certain the differences in memory speed will significantly exceed any realistic multi-hop interconnect latency.

tier support exist already in a fashion

Posted May 29, 2026 20:14 UTC (Fri) by hahn (subscriber, #172848) [Link]

Hello, I'm Joshua Hahn (presenter of the article's subject). Thank you for your interest in my work!

> I was also wondering how this "tiering" was not covered by NUMA.

So both you and clameter are right in that NUMA abstractions already present a way to allocate memory differently based on performance (see: weighted interleave [1]). More explicitly, "memory tiers" have been around for quite a while and already do a great job of separating nodes based on their performance characteristics, and "tiering" (moving memory around between these tiers via demotion and promotion) is something that is also an area that is being investigated by many MM developers too!

So yes, tiering already exists and there is a lot of support for it. But what I'm hoping to do in this work is to build on top of that work, and add a new dimension by introducing "fair tiering" across memcgs. That is, how can you prevent one memcg from hogging all of the high-performance nodes? As far as I can tell, tiering mechanisms currently do not offer fairness across memcgs and operate on a host-wide granularity.

> Another possible issue is that the perception of tiering may *not* be globally uniform.

This is a great point, and there is some ongoing work to better capture this [2]. With that said, from a tiering perspective I think your following comment is accurate:

> A graph potentially may be a better abstraction than a hierarchy, unless it's fairly certain the differences in memory speed will significantly exceed any realistic multi-hop interconnect latency.

For the systems that I had in mind while developing this work, we are talking about the toptier memory living in DRAM, while the lowtier refers to CXL. And there's some nontrivial latency differences between the two nodes. (Also, the CXL node is CPUless, so there's only one "local" node in the system. The question becomes a bit more sticky with multi-socket CXL systems though...)

Thank you both for your interest, and thank you Jonathan for the great article and a forum to continue the discussion : -)
Joshua

[1] https://lwn.net/Articles/969379/
[2] https://lore.kernel.org/linux-mm/20260316051258.246-1-rak...

Such a system already exists

Posted May 28, 2026 14:13 UTC (Thu) by neggles (subscriber, #153254) [Link]

Intel made a number of Xeon Max SKUs (primarily for the Aurora supercomputer) with on-package HBM as well as off-package DDR5, and Fujitsu have an upcoming HPC CPU (Monaka-X) which will have HBM, DDR5, and accelerator memory pools, for example


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