| From: |
| Akhil P Oommen <akhilpo-AT-oss.qualcomm.com> |
| To: |
| Rob Clark <robin.clark-AT-oss.qualcomm.com>, Sean Paul <sean-AT-poorly.run>, Konrad Dybcio <konradybcio-AT-kernel.org>, Dmitry Baryshkov <lumag-AT-kernel.org>, Abhinav Kumar <abhinav.kumar-AT-linux.dev>, Jessica Zhang <jesszhan0024-AT-gmail.com>, Marijn Suijten <marijn.suijten-AT-somainline.org>, David Airlie <airlied-AT-gmail.com>, Simona Vetter <simona-AT-ffwll.ch>, Antonino Maniscalco <antomani103-AT-gmail.com>, Connor Abbott <cwabbott0-AT-gmail.com>, Maarten Lankhorst <maarten.lankhorst-AT-linux.intel.com>, Maxime Ripard <mripard-AT-kernel.org>, Thomas Zimmermann <tzimmermann-AT-suse.de> |
| Subject: |
| [PATCH v2 00/17] drm/msm: A8xx Support - Batch 2 |
| Date: |
| Fri, 27 Mar 2026 05:43:49 +0530 |
| Message-ID: |
| <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com> |
| Cc: |
| linux-arm-msm-AT-vger.kernel.org, dri-devel-AT-lists.freedesktop.org, freedreno-AT-lists.freedesktop.org, linux-kernel-AT-vger.kernel.org, Akhil P Oommen <akhilpo-AT-oss.qualcomm.com>, Konrad Dybcio <konrad.dybcio-AT-oss.qualcomm.com> |
| Archive-link: |
| Article |
This series brings a few additional features for A8xx GPUs which were
deferred in the initial series. First few patches are a few general fixes
and improvements. The next few patches adds support for SKU tables,
Preemption, IFPC and a UABI to query AQE support.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Changes in v2:
- Split X2-85 SKU detection patch (Rob)
- Split out a7xx_gmu_gx_is_on() (Konrad)
- Avoid secure init on every gmu_resume (Konrad)
- Simplify code in adreno_load_gpu() using guard(mutex) (Konrad)
- Correct the payload size for CP_ME_INIT packet (Konrad)
- Remove unnecessary gmu_wrapper check in a8xx_preempt.c (Konrad)
- Few misc formatting fixes (Konrad/Claude bot)
- Add Fixes tag & reorder patches to move fixes to top (Rob/Dmitry)
- Captured R-b tags
- Link to v1: https://lore.kernel.org/r/20260324-a8xx-gpu-batch2-v1-0-f...
---
Akhil P Oommen (17):
drm/msm/a6xx: Use barriers while updating HFI Q headers
drm/msm/a8xx: Fix the ticks used in submit traces
drm/msm/a6xx: Switch to preemption safe AO counter
drm/msm/a6xx: Correct OOB usage
drm/msm/adreno: Implement gx_is_on() for A8x
drm/msm/a6xx: Fix gpu init from secure world
drm/msm/a6xx: Add support for Debug HFI Q
drm/msm/adreno: Coredump on GPU/GMU init failures
drm/msm/a6xx: Use packed structs for HFI
drm/msm/a6xx: Update HFI definitions
drm/msm/a8xx: Add SKU table for A840
drm/msm/a6xx: Add soft fuse detection support
drm/msm/a6xx: Add SKU detection support for X2-85
drm/msm/a8xx: Implement IFPC support for A840
drm/msm/a8xx: Preemption support for A840
drm/msm/a6xx: Enable Preemption on X2-85
drm/msm/adreno: Expose a PARAM to check AQE support
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 6 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +-
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 243 +++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 141 ++++++++++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 9 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 169 +++++++-------
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 7 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 6 +-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 ++-
drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 155 +++++++++++--
drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 77 +------
drivers/gpu/drm/msm/adreno/a6xx_preempt.h | 82 +++++++
drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 162 ++++++++++++--
drivers/gpu/drm/msm/adreno/a8xx_preempt.c | 259 ++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 20 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +-
drivers/gpu/drm/msm/msm_gpu.c | 5 +-
drivers/gpu/drm/msm/msm_gpu.h | 2 +
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4 +
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 6 +-
include/uapi/drm/msm_drm.h | 1 +
23 files changed, 1137 insertions(+), 273 deletions(-)
---
base-commit: 38d568f154c66430920b01edc9c722ec14aa54d7
change-id: 20260322-a8xx-gpu-batch2-bf7f5a9406ac
Best regards,
--
Akhil P Oommen <akhilpo@oss.qualcomm.com>
