| From: |
| Geetha sowjanya <gakula-AT-marvell.com> |
| To: |
| <linux-perf-users-AT-vger.kernel.org>, <linux-kernel-AT-vger.kernel.org>, <linux-arm-kernel-AT-lists.infradead.org>, <devicetree-AT-vger.kernel.org> |
| Subject: |
| [PATCH 0/2] perf: marvell: Add CN20K DDR PMU support |
| Date: |
| Thu, 26 Mar 2026 14:36:43 +0530 |
| Message-ID: |
| <20260326090645.22590-1-gakula@marvell.com> |
| Cc: |
| <mark.rutland-AT-arm.com>, <will-AT-kernel.org>, <krzk+dt-AT-kernel.org> |
| Archive-link: |
| Article |
This series adds support for the Marvell CN20K DRAM Subsystem (DSS)
performance monitor in the existing marvell_cn10k_ddr_pmu driver, and
documents the device tree binding for the new compatible string.
The CN20K PMU provides eight programmable counters and two fixed
counters (DDR reads and writes). Patch 1 adds the devicetree schema for
"marvell,cn20k-ddr-pmu". Patch 2 wires OF and ACPI (MRVL000B) match
entries, adds CN20K register offsets and event maps, and refactors
platform data to use silicon variant flags.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Geetha sowjanya (2):
dt-bindings: perf: marvell: Document CN20K DDR PMU
perf: marvell: Add CN20K DDR PMU support
.../bindings/perf/marvell-cn20k-ddr.yaml | 37 ++++
drivers/perf/marvell_cn10k_ddr_pmu.c | 186 ++++++++++++++++--
2 files changed, 207 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
--
2.25.1
