| From: |
| Biju <biju.das.au-AT-gmail.com> |
| To: |
| Thomas Gleixner <tglx-AT-kernel.org>, Rob Herring <robh-AT-kernel.org>, Krzysztof Kozlowski <krzk+dt-AT-kernel.org>, Conor Dooley <conor+dt-AT-kernel.org>, Geert Uytterhoeven <geert+renesas-AT-glider.be>, Magnus Damm <magnus.damm-AT-gmail.com> |
| Subject: |
| [PATCH 0/8] Add RZ/G3L IRQC support |
| Date: |
| Wed, 04 Feb 2026 14:23:08 +0000 |
| Message-ID: |
| <20260204142320.103184-1-biju.das.jz@bp.renesas.com> |
| Cc: |
| Biju Das <biju.das.jz-AT-bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj-AT-bp.renesas.com>, linux-kernel-AT-vger.kernel.org, devicetree-AT-vger.kernel.org, linux-renesas-soc-AT-vger.kernel.org, Biju Das <biju.das.au-AT-gmail.com> |
| Archive-link: |
| Article |
From: Biju Das <biju.das.jz@bp.renesas.com>
The IRQC block on RZ/G3L SoC is almost identical to one found on the
RZ/G3S SoC with the difference like it support more External IRQs, GPT
Error Interrupts and also has additional registers for GPT/MTU IRQ
selection, shared IRQ selection between external IRQ and TINT.
It has 16 external interrupts of which 8 interrupts are shared with
TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
selection is based on a register in the ICU block.
Biju Das (8):
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L
SoC
irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct
rzg2l_irqc_priv
irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
irqchip/renesas-rzg2l: Add RZ/G3L support
irqchip/renesas-rzg2l: Add shared irq support
arm64: dts: renesas: r9a08g046: Add ICU node
.../renesas,rzg2l-irqc.yaml | 66 +++++-
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 91 ++++++++
drivers/irqchip/irq-renesas-rzg2l.c | 218 +++++++++++++++---
3 files changed, 343 insertions(+), 32 deletions(-)
--
2.43.0
