| From: |
| Biju <biju.das.au-AT-gmail.com> |
| To: |
| Geert Uytterhoeven <geert+renesas-AT-glider.be>, Michael Turquette <mturquette-AT-baylibre.com>, Stephen Boyd <sboyd-AT-kernel.org> |
| Subject: |
| [PATCH v2 0/4] Add support for Renesas RZ/G3L GBETH clocks |
| Date: |
| Fri, 30 Jan 2026 11:58:41 +0000 |
| Message-ID: |
| <20260130115850.253555-1-biju.das.jz@bp.renesas.com> |
| Cc: |
| Biju Das <biju.das.jz-AT-bp.renesas.com>, linux-renesas-soc-AT-vger.kernel.org, linux-clk-AT-vger.kernel.org, linux-kernel-AT-vger.kernel.org, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj-AT-bp.renesas.com>, Biju Das <biju.das.au-AT-gmail.com> |
| Archive-link: |
| Article |
From: Biju Das <biju.das.jz@bp.renesas.com>
Add support for Renesas RZ/G3L GBETH clocks and reset signals.
v1->v2:
* Separated ethernet patches from series [1]
This patch series is depend upon [2]
[1] https://lore.kernel.org/all/20260128125850.425264-1-biju....
[2] https://lore.kernel.org/all/20260128113032.337231-1-biju....
Biju Das (4):
clk: renesas: rzg2l: Drop a check in rzg3s_cpg_pll_clk_recalc_rate()
clk: renesas: rzg2l: Add support for enabling PLLs
clk: renesas: r8a08g046: Add support for PLL6 clk
clk: renesas: r9a08g046: Add clock and reset signals for the GBETH IPs
drivers/clk/renesas/r9a08g046-cpg.c | 120 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.c | 70 +++++++++++++++-
drivers/clk/renesas/rzg2l-cpg.h | 10 +++
3 files changed, 197 insertions(+), 3 deletions(-)
--
2.43.0
