| From: |
| Ovidiu Panait <ovidiu.panait.rb-AT-renesas.com> |
| To: |
| biju.das.jz-AT-bp.renesas.com, geert+renesas-AT-glider.be, magnus.damm-AT-gmail.com, robh-AT-kernel.org, krzk+dt-AT-kernel.org, conor+dt-AT-kernel.org, mturquette-AT-baylibre.com, sboyd-AT-kernel.org |
| Subject: |
| [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK |
| Date: |
| Tue, 21 Oct 2025 17:53:07 +0000 |
| Message-ID: |
| <20251021175311.19611-1-ovidiu.panait.rb@renesas.com> |
| Cc: |
| linux-renesas-soc-AT-vger.kernel.org, devicetree-AT-vger.kernel.org, linux-kernel-AT-vger.kernel.org, linux-clk-AT-vger.kernel.org |
| Archive-link: |
| Article |
Hi,
This series extends the versaclock3 driver to support the internal
freerunning 32.768 kHz clock, which is used on the RZ/V2H SoC as RTC
counter clock. It also adds the dts node for the RZ/V2H EVK.
Best regards,
Ovidiu
Ovidiu Panait (4):
clk: versaclock3: Remove unused SE2 clock select macro
clk: versaclock3: Use clk_parent_data arrays for clk_mux
clk: versaclock3: Add freerunning 32.768kHz clock support
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock
generator node
.../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 25 ++++
drivers/clk/clk-versaclock3.c | 126 +++++++++++++-----
2 files changed, 120 insertions(+), 31 deletions(-)
--
2.51.0
