http://lwn.net/Articles/254445/ This is a special feed containing comments posted to the individual LWN article titled "Memory part 4: NUMA support". hourly 2 http://lwn.net/Articles/264585/rss 2008-01-10T14:27:44+00:00 rengolin <div class="FormattedComment"><pre> <font class="QuotedText">&gt; a radius 1 arrangement can actually include 3 CPUs, think a triangle, every machine is at most one hop from the memory</font> Actually it's N+1 being N the number of dimensions you build your computer. In the three-dimensional reality a tetrahedron (4CPUs) is radius 1, in the two-dimensional a triangle and so on, therefore we can increase the number of CPUs in radius 1 by building computers in higher dimensions! ;) </pre></div> http://lwn.net/Articles/256207/rss 2007-10-27T06:51:09+00:00 dlang it's also possible to have a radius-3 arrangement with only 3 links <br><pre> 1--2-- | | | 3--4 | | | | 5--6 | | | | 7--8-- </pre><br> this leaves CPU's 1 and 7 with an extra link available for connections to a southbridge. http://lwn.net/Articles/255863/rss 2007-10-25T12:47:08+00:00 joib <i> the Opteron already has versions that have four HT links, they are the 800/8000 series chips targeted at 8 cpu systems </i> <p> That is not correct. All current Opterons (including the 800(0) series) have 3 HT links. The difference is that in the 800(0) series all 3 HT links are cache coherent, whereas there is only one cache coherent link on the 200(0) series and none on the 100(0) series (and athlon64). <p> That being said, the recently released quad core Opterons do in principle support 4 HT links, but so far they are using the existing socket so they are limited to 3 links until the next generation socket is introduced. http://lwn.net/Articles/255293/rss 2007-10-22T00:35:12+00:00 dlang <pre class="FormattedComment"> several comments a radius 1 arrangement can actually include 3 CPUs, think a triangle, every machine is at most one hop from the memory the Opteron already has versions that have four HT links, they are the 800/8000 series chips targeted at 8 cpu systems </pre> http://lwn.net/Articles/255112/rss 2007-10-19T04:47:10+00:00 sweikart <pre class="FormattedComment"> Intel is working on a point-to-point processor interconnect called QuickPath, which is a competitor to AMD's HyperTransport. AMD will support HyperTransport 3.0 with its next-generation sockets (AM2+ and F+). HyperTransport 3.0 lets you split the links in half, so you can have 8 links total (and HT3.0 links can run twice as fast as HT2.0 links, so the half-width links should have good throughput). I assume this will enable a fully-connected (diameter of 1) eight-socket server. </pre> http://lwn.net/Articles/254969/rss 2007-10-18T13:33:18+00:00 dany <pre class="FormattedComment"> Thanks for another very informative article! I am wondering, in relevant opteron CPU measured, how much slower are read/write operations on remote memory 2-hops away (figure 5.4 is about 1 hop away remote memory)? </pre>