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Kernel Summit: Processor panelKernel Summit: Processor panelPosted Jul 22, 2004 19:12 UTC (Thu) by jzbiciak (✭ supporter ✭, #5246)Parent article: Kernel Summit: Processor panel On the dual-core processor issue: It's kinda interesting, actually. Some operations potentially get faster, and some get slower. Consider variables shared across CPUs, such as locks and kernel data structures. As long as the chip is smart enough to forward snoops among the CPUs and not send the data out on the pins, the performance of cache line "ping pong" could go up (cycle count go down). On a separate note, I wonder if any CPU vendors are considering an on-chip L3 that would be shared among the multiple cores? This could reduce some of the contention issues, depending on how you do it. You'd still have contention for L3, but L3 hits would be serviced much more quickly than accesses off-chip. Thus, the /length/ of the contention is less. Furthermore, there are tricks you can pull to reduce the amount of time you're contended, such as banking your memory aggressively.
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