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A handful of DMA topicsA handful of DMA topicsPosted Jun 24, 2004 14:30 UTC (Thu) by mmarkov (subscriber, #4978)Parent article: A handful of DMA topics Meanwhile, Ian Molton turned up a different sort of problem. Some types of interfaces have their own onboard memory. This memory is, often, accessible to the CPU, How does the CPU access this memory? Via the data bus? What addresses does it use -- and aren't all the valid addresses refering to the RAM?
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A handful of DMA topics Posted Jun 24, 2004 16:06 UTC (Thu) by Duncan (guest, #6647) [Link] Wouldn't a graphics card be the best known of these? I haven't read themain article as I'm just skimming them now to come back to later (after some sleep, when I can make better sense of them <g>), so I don't know if that fits in the context or not, but it's immediately what *I* think of when I think of an interface with its own memory. Duncan
A handful of DMA topics Posted Jun 25, 2004 14:38 UTC (Fri) by cthulhu (guest, #4776) [Link] Check out Ian's email - the chip memory is in the CPU I/O address space.If it accessible in the PCI or AGP space, it would show up in the CPU memory space. What I'm wondering now is how such chips have been used by drivers in the past. My guess is that there were alternatives to using the I/O space, or they didn't use DMA. In this case, the chip *must* DMA from its own internal memory, and hence forced this enhancement.
A handful of DMA topics Posted Jul 1, 2004 12:49 UTC (Thu) by jamey (guest, #22733) [Link] For the devices for which Ian and I are writing drivers, the CPU accesses the device's internal memory via the CPU memory bus. On other platforms, the CPU might access the internal memory via an IO bus. The new DMA calls proposed by James Bottomley (dma_declare_coherent_memory and dma_release_coherent_memory) handle either case.Many drivers for such devices used ioremap and private memory allocators. What caused us to propose this change was the use of standard device hardware interfaces (UCB OHCI) in the context of a chip with direct access only to private SRAM. In the past, we made extensive modifications to drivers such as the USB OHCI driver to support these devices. However, it appeared that the 2.6 device model and the generic DMA API would enable us to clean this up and to produce drivers acceptable to the mainstream kernel.
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