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Deadline scheduling: coming soon?
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Given that people don't even bother to define what acceptable input is, I don't expect this to ever happen.
Not to mention that this would require anticipating all possible internal state, another thing that is not going to happen.
And then you need to have someone think through what should happen in all these combinations of cases, and not have any logic errors in what the 'proofs' are trying to show.
> Hardware design developed formal method for their logic ALUs and FPUs a long time ago. Although that clearly has it's limits. Especially timing.
And when Timing issues dominate, the 'correctness' generated by such proofs is pretty meaningless.
Math is not reality, they sometimes have a resemblance to each other, but that's just a happy coincidence.
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