GCC and static analysis
Posted Apr 30, 2012 15:10 UTC (Mon) by khim
In reply to: GCC and static analysis
Parent article: GCC and static analysis
Why? Async chips do not depend (strongly) on the speed of light.
Async has huge PR value (you can claim you chip is working on 100GHz or even 1THz if you are lucky). It does not change anything WRT to actual speed of computation.
One part of an async chip can be doing completely unrelated tasks.
It's the same with synchronous schemes as well. Why do you think Prescott had over 30 stages in pipeline? Why do you think Itanic has L1, L2 and L3 caches - all on the same chip with the same semiconductor process technology?
Of course, in the end you'll hit the lightspeed wall, but it's a long way off.
In the end the nominal number on the CPU envelope is just a number. Sure, you can create totally-async 1THz chip which will need "about 1000 tics" to add two numbers together, but it'll be slower then Core i7 so what's the point? Lightspeed barrier it as real for async as it's for traditional CPU.
Note that lightspeed barrier only limits latency (of single-threaded program in this particular case), it does not affect throughput at all. In fact a way to create tremendous throughput is well known: just use more of the same things!
So? Modern network routers work at about the same speed and die size.
They don't execute sequential program, that's totally different kettle of fish. For them streaming async design makes perfect sense. For GPUs it can be applied, too. For CPUs? Not so much. Netburst tried to do that. It failed. I doubt anyone will actually try to do it again.
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