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Ivy Bridge first Intel processor with digital hardware random number generatorIvy Bridge first Intel processor with digital hardware random number generatorPosted Mar 30, 2012 15:17 UTC (Fri) by jhardin (guest, #3297)In reply to: Ivy Bridge first Intel processor with digital hardware random number generator by jhhaller Parent article: Russell: Sources of Randomness for Userspace
I've always wondered why a 4- or 8-bit register incremented on every clock cycle wouldn't be a simple yet good enough source of entropy? How often is it going to be read?
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Ivy Bridge first Intel processor with digital hardware random number generator Posted Apr 2, 2012 12:52 UTC (Mon) by jzbiciak (✭ supporter ✭, #5246) [Link]
That was a fine source of randomness for, say the MIPS TLB random replacement, especially since page faults are "far apart," typically.
What about the kernel entropy pool though? First off, where are you sampling this counter to give you data to mix into the pool? Interrupts? With periodic interrupts, you can probably only trust the LSB of the counter to be truly random. That leaves you generating only hundreds or thousands of bits per second.
In any case, on most modern CPUs, we have this freerunning counter already. On x86, it's called the TSC. Of course, it appears RDTSC can get mucked up by virtualization.
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