Posted Mar 23, 2012 5:07 UTC (Fri) by jcm (subscriber, #18262)
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Do bear in mind in these numbers that we're currently building on PandaBoards, TrimSlices, and the like. They have nothing like the many MB of L2 cache you're going to see in real 32-bit ARM servers in the coming months, which will also have much improved on-chip IO. I actually think the 2-2.5x speedup estimates we've been given will end up being low because for IO bound operation we're going to have up to 4x the cache, 4x the RAM, and a lot of other microarchitectural improvements.
2 hour ARM build
Posted Mar 23, 2012 10:59 UTC (Fri) by etienne (subscriber, #25256)
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> real 32-bit ARM servers ... 4x the cache, 4x the RAM
With the ARM instruction set, unless using Thumb, you have each instruction coded on 32 bits, so 256 assembly instructions weight 1 Kbyte.
You will need a lot more code cache than a ia32 processor to compete, probably around twice the amount.
2 hour ARM build
Posted Mar 24, 2012 5:19 UTC (Sat) by BenHutchings (subscriber, #37955)
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