"it could use the big hammer of a full cache flush before unlock.
Cache coherency is really just a crutch. Lots of embedded programmers and Cell programmers (no cache protocol on the SPE's) know how to work without it. :-)"
Full cache flush == embedded "Big Kernel Lock" equivalent?
Posted Feb 19, 2012 21:51 UTC (Sun) by phip (guest, #1715)
[Link]
Big Kernel Lock...
Hmm, that brings up another point I should have thought of earlier:
Non-coherent multi-CPU SOCs are also likely to not implement
atomic memory access primatives (i.e. Compare/Exchange, Test and Set,
Load-Linked/Store-Conditional, etc.)