| |||||||||||||
Intel's upcoming transactional memory featureIntel's upcoming transactional memory featurePosted Feb 9, 2012 17:53 UTC (Thu) by kjp (subscriber, #39639)In reply to: Intel's upcoming transactional memory feature by josh Parent article: Intel's upcoming transactional memory feature
Yeah. This post explains the big picture a lot better.
http://software.intel.com/en-us/blogs/2012/02/07/coarse-g...
HLE looks pretty cool, just wondering how large a 'transaction' can be in practice. If it gets too big I guess the cpu can just abort and force a lock.
(Log in to post comments)
Intel's upcoming transactional memory feature Posted Feb 10, 2012 6:56 UTC (Fri) by Tuna-Fish (subscriber, #61751) [Link]
The practical limit is most likely that the transaction needs to fit in it's entirely in L1 cache. At first, that sounds like a lot (16kBish per thread), but remember that the L1 cache is typically only 8-way. So, as long as accesses don't align badly you can touch quite a bit of memory without issue, but when you do the 9th access at a 4k alignment, it faults. (or likely *before* that -- the system will very likely want to leave some ways for the other thread.)
Intel's upcoming transactional memory feature Posted Feb 10, 2012 19:03 UTC (Fri) by Ben_P (guest, #74247) [Link]
How small can transactional regions be? Hopefully smaller than a page?
Intel's upcoming transactional memory feature Posted Feb 10, 2012 19:12 UTC (Fri) by josh (subscriber, #17465) [Link]
As small as one cache line, as far as I can tell. The spec mentions that other operations within the same cache line may cause spurious transaction conflicts.
|
|||||||||||||