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And often a machine implements the smaller accesses but there is a performance penalty due to alignment issues and the bus/DRAM access architecture. It's not uncommon for the RMW to be faster.
Betrayed by a bitfield
Posted Feb 8, 2012 13:57 UTC (Wed) by nix (subscriber, #2304)
It's actually easier to come up with a list of architectures that do *not* require natural alignment on loads and stores than to come up with a list of those that do.
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