PARALLEL Input Output controller (PIO) is what Atmel call the silicon subsystem in their AT91 family of SOCs that control gpio lines. I'm familiar with the AT91SAM9G20 and the G20 has 3 controllers while the G45 has 5 of them. Each is 32 bits wide (so the G20 has 3*32=96 GPIO lines).
Now the kernel's existing approach based on gpiolib is a sick joke, as it is based on abstracting all the complexity (explained in your article) out of the gpio architecture, so what is left is lame.
So the bit I wanted to stress in this post is that gpio lines in the same controller bank (i.e. 32 lines) can be used as a parallel bus. In the hardware I use PC16-PC31 are used as the top 16 bits of the data bus. Now not many users should be fiddling with the data bus but there are other uses of the parallel nature of some gpio lines. A step too far for a pin control system?
If so then mmap() is your friend. As the SCSI storage subsystem has taught me: the kernel isn't necessarily the way, it often is in the way.