|| ||Robert Richter <firstname.lastname@example.org> |
|| ||Peter Zijlstra <email@example.com> |
|| ||[PATCH 0/7 -v2] perf, x86: Implement AMD IBS |
|| ||Wed, 7 Sep 2011 18:36:09 +0200|
|| ||Ingo Molnar <firstname.lastname@example.org>, Stephane Eranian <email@example.com>,
|| ||Article, Thread
This patch set adds support for AMD IBS to perf. It is a new
implementation and unrelated to my previous postings last year. The
main differences are:
* separate and independent from x86 perfctrs, IBS could be used
without the x86 pmu,
* using dynamic pmu allocation, userspace uses sysfs to select the pmu,
* support for 64 bit counters,
* libperf based example code,
* shared IBS initialziation code for perf and oprofile.
The approach is still to collect raw sample data which should be the
most important use case for application developers. The data format is
the same as described in the IBS register specification.
Future work could be:
* better integration into the perf tool, use IBS for generic events
* support of the precise event sampling perf i/f,
* implementation of extended IBS features (e.g. ext. counter width),
* support of counting (perf stat),
* in-kernel IBS event parsing,
* IBS tracepoint support.
Changes for V2:
* Remove printks in pmu function stubs.
* Modify perf_event_ibs_init() to use ibs_caps directly.
* Added bit mask for msr offsets.
* Added caps field to raw sample format.
* Added caps check for IBS_OP_CUR_CNT emulation.
* Updated include header files to fix build errors on some distros.
* Note: I kept example code for reference, the patch must not be
applied. I will come up with a sulution that integrates IBS into
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