You may have just been lucky that the most voltage-sensitive circuits were active in the "upper" region you excluded. It's not likely that the memory was statically powered down because it wasn't in use, but there are many dynamic power loads in digital circuits as they change states.
It could even have to do with certain combinations of address and data bits that required more power to configure the addressing logic and route the data signals, and it didn't stabilize within the configured access timings.
The end result is that certain memory addresses in a given module will tend to show corruption before others as the power supply sags or the timings get too tight. This is why people advocate long runs with a dedicated memory test program to try to validate parts in situ. Just running an OS may not exercise combinations of address and data bits with sufficient testing coverage, at least not for many hours (or weeks!) of operation.