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Memory power management power savings testMemory power management power savings testPosted Jun 11, 2011 3:19 UTC (Sat) by willy (subscriber, #9762)In reply to: Memory power management power savings test by etienne Parent article: Memory power management
The problem is that pages are interleaved across DIMMs. If you have 3 channels with a single DIMM each, cacheline 0 is on DIMM 0, cacheline 1 on DIMM 1, cacheline 2 on DIMM 2 and cacheline 3 on DIMM 0. Removing a DIMM causes the interleaving to change, which will also cause performance to change, and your measurements are now invalid.
As I understand PASR, one would not power down an entire DIMM, but rather sections of each DIMM, thus preserving the performance benefits of interleaving.
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Memory power management power savings test Posted Jun 16, 2011 4:54 UTC (Thu) by Ankita (subscriber, #39147) [Link]
Yes, PASR support seems to be at bank level. From a few documents I have read, I find that interleaving can be configured to control the number of banks that have to be kept open for every memory access, typically the minimum being 2 banks. Thus, if only two banks are interleaved, the other banks can potentially be turned off or not refreshed. Power v performance benchmarking will be needed to decide on the best interleaving scheme though.
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