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MIPS Technologies Launches New Developer Community
MIPS Technologies Launches New Developer Community
Developer.mips.com Offers Comprehensive Development Resources
for the MIPS(R) Architecture
SUNNYVALE, Calif., April 14, 2011 (GLOBE NEWSWIRE) -- MIPS
Technologies, Inc. (Nasdaq:MIPS), a leading provider of
industry-standard processor architectures and cores for digital home,
networking and mobile applications, today announced the launch of its
new Developer Community at Developer.mips.com. The new site, which is
live now, is specifically tailored to the needs of software developers
working with the Android(TM) platform, Linux operating system and other
applications for MIPS-Based(TM) hardware. All information and resources
on the site are openly accessible.
"This new community demonstrates our ongoing commitment to the vibrant
open source effort around the MIPS cores and architecture, as well as
around our customers' and their customers' hardware platforms," said
Art Swift, vice president of marketing and business development, MIPS
Technologies. "As the MIPS architecture continues to expand into new
high-volume markets such as mobile handsets and tablets, we see an
increasing need for these resources among the growing MIPS developer
community."
On the site, developers will find resources including:
-- Android on MIPS source code, porting instructions, a native development
kit (NDK) for Android applications development on MIPS, and other
Android resources
-- Linux on MIPS resources including kernel source code
-- Downloadable development tools including the MIPS Navigator(TM)
Integrated Component Suite (ICS) integrated development environment and
GCC compilers for MIPS
-- How-to video tutorials for MIPS Navigator ICS including the "Multicore
Debug Series"
-- Access to EJTAG debugger tools
-- Information about MIPS-Based development boards
-- Application notes and support forums for Android, Linux and developer
tools
-- Blog postings from MIPS development engineers on developer-specific
topics such as kernels, performance tuning and debug tips/tricks
-- Links to other MIPS community sites including mipsandroid.org and
linux-mips.org
-- Information about other MIPS ecosystem companies and resources
Visit http://developer.mips.com to join the MIPS Developer Community.
About MIPS Technologies, Inc.
MIPS Technologies, Inc. (Nasdaq:MIPS) is a leading provider of
industry-standard processor architectures and cores that power some of
the world's most popular products for the digital home, networking and
mobile device markets. These include broadband devices from Linksys,
DTVs and digital consumer devices from Sony, DVD recordable devices
from Pioneer, digital set-top boxes from Motorola, network routers from
Cisco, 32-bit microcontrollers from Microchip Technology and laser
printers from Hewlett-Packard. Founded in 1998, MIPS Technologies is
headquartered in Sunnyvale, California, with offices worldwide. For
more information, contact (408) 530-5000 or visit www.mips.com.
Follow MIPS on Facebook, LinkedIn, YouTube, RSS and Twitter.
MIPS and MIPS-Based are trademarks or registered trademarks in the
United States and other countries of MIPS Technologies, Inc. All other
trademarks referred to herein are the property of their respective
owners. Android is a trademark of Google Inc. Use of this trademark is
subject to Google Permissions.
CONTACT: Media Contacts:
Jen Bernier-Santarini
MIPS Technologies, Inc.
+1 408-530-5178
jenb@mips.com
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MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 2:27 UTC (Fri) by mfedyk (guest, #55303) [Link]
Good, I've been wondering why arm gets so much use when mips is already 64 bit and low power
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 5:51 UTC (Fri) by ncm (subscriber, #165) [Link]
Curiously, it's partly because the MIPS memory model is almost incompatible with shared-memory multiprocessing. Amusingly, MIPS, Alpha, PowerPC, and Itanic are incapable of implementing Java's notion of shared memory without kernel interaction. x86's slips under the wire by imposing crippling overheads on large-N multiprocessors. When we get shared-memory machines with more than (say) 8 processors, x86's overhead will get too large, and a lot of programs you thought were right won't be. You can experiment with the sort of failures you will encounter by running on a dual-CPU MIPS.
The effect will be that you cannot count on any other thread seeing changes you make in shared memory -- it might see some changes, but not others made earlier -- until after both you and the other processor each take a mutex or other IPC gadget. Goodbye global flags.
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 7:42 UTC (Fri) by ajb (subscriber, #9694) [Link]
That's interesting - do you have a link to something which goes into more detail?
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 23:22 UTC (Fri) by ncm (subscriber, #165) [Link]
The ISO C++ Standard committee finally picked up the baton and codified implementable memory model requirements. The C committee promised to match them in their next standard. As I recall, of common architectures only the MIPS spec is actually incompatible, in that it doesn't provide the minimal guarantees a programmer needs to get predictable results. Java's memory model makes promises real machines can't satisfy without crippling multi-processor performance.
Actual MIPS machines may provide stronger guarantees than the MIPS architecture promises, just as actual C compilers usually roll signed ints over to a negative value even though they are within their rights to erase your disk and send a threatening e-mail to the president. It's entirely possible that Daney's Java programs do not actually depend on Java's more extreme (and likely unmet) promises, or even that he just hasn't identified the source of intermittent mysterious problems.
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 23:59 UTC (Fri) by daney (subscriber, #24551) [Link]
The MIPS architecture is not a single fixed specification. There is a series of architecture revisions that add more and more features. Similar to how Intel et al. keep adding things to the i386 architecture.
As far as I know the C++ memory model can be satisfied by standard memory barrier facilities. All modern MIPS architecture CPUs have a memory barrier (the SYNC instruction) and more recent revisions of the architecture specification have a more extensive set of memory barrier variants.
And my java programs run in the libgcj runtime environment, which implements the java memory model, so there have been no 'mysterious' problems.
MIPS Technologies Launches New Developer Community Posted Apr 16, 2011 21:53 UTC (Sat) by cmccabe (guest, #60281) [Link]
Speaking of C/C++ memory models, does anyone know what the resolution was for this?
http://lkml.org/lkml/2007/10/24/673
I keep reading the thread, but nobody proposes an actual fix. Is pthread_trylock just broken under gcc?
MIPS Technologies Launches New Developer Community Posted Apr 17, 2011 11:01 UTC (Sun) by kevinm (guest, #69913) [Link]
I cannot find an authoritative reference, but testing on gcc 4.4.5 shows that the problematic optimisation seems to have been removed.
(It's not just pthread_trylock(), or even threads - that optimsation won't even play well with mprotect() in the single-threaded case!)
MIPS Technologies Launches New Developer Community Posted Apr 17, 2011 11:22 UTC (Sun) by kevinm (guest, #69913) [Link]
Actually, Andrew Haley confirmed that a fix for the bug was checked in to gcc here:
http://lkml.indiana.edu/hypermail/linux/kernel/0710.3/303...
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 8:22 UTC (Fri) by mti (subscriber, #5390) [Link]
Java by itself has a really weak memory ordering model. Do you mean something else by "shared memory" than just accessing the same variables from multiple threads?
Or do you just mean that MIPS et al can't run broken programs, that is cannot run programs that assume a stronger ordering than Java guaranties?
MIPS Technologies Launches New Developer Community Posted Apr 16, 2011 4:07 UTC (Sat) by wahern (subscriber, #37304) [Link]
I don't do much assembly, but I presume he's referring to the fact that on x86 many simple operations often have guaranteed globally ordered behavior even without any explicit synchronization.
For a summary: http://bartoszmilewski.wordpress.com/2008/11/05/who-order...
See also section 8.2 in Intel's manual: http://www.intel.com/Assets/PDF/manual/253668.pdf
I also presume he's saying that for some very sophisticated memory architectures in order to get any of the global guarantees that shared memory "threaded" languages expect you have to communicate with special hardware. For such systems message passing methods are probably the preferred way to share state. Which would suit me just fine because even in C this is my preferred pattern.
MIPS Technologies Launches New Developer Community Posted Apr 17, 2011 9:24 UTC (Sun) by mti (subscriber, #5390) [Link]
Yes you are right that x86 has a stronger memory ordering than e.g. MIPS. Many multi-threaded programs fail when ported from x86 to other platforms because of this.
The thing is that the Java JVM has a really weak memory ordering. I might be wrong but I cannot find any reason why it would be hard to implement a fast JVM on MIPS.
The problem might be that even though the JVM is correct the programs running on it might not be correct. Running a Java program on an x86 JVM might hide some bugs that are exposed by running the same program on a MIPS JVM.
Btw, I also prefer message passing since it's just so much simpler than sharing memory.
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 16:42 UTC (Fri) by daney (subscriber, #24551) [Link]
> Curiously, it's partly because the MIPS memory model is
> almost incompatible with shared-memory multiprocessing.
What in the world are you talking about?
> Amusingly, MIPS, Alpha, PowerPC, and Itanic are incapable of
We regularly run 16 and 32 processor SMP MIPS machines and java.
There is a long history of SMP MIPS machines that work just fine.
MIPS Technologies Launches New Developer Community Posted Apr 18, 2011 2:07 UTC (Mon) by aaron (subscriber, #282) [Link]
Interesting. How did SGI do it, then?
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 7:31 UTC (Fri) by renox (subscriber, #23785) [Link]
> Good, I've been wondering why arm gets so much use when mips is already 64 bit and low power
Plus MIPS has trap on overflow for integer computations which is nice for Ada.
But I don't think that ARM is winning due to a technical advantage, I think that this is probably because the owners of ARM are better businessmen..
Note that MIPS could see a revival with Loongson.
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 9:54 UTC (Fri) by tuxmania (guest, #70024) [Link]
Im also pretty interested in China's work on Loongson and how it may alter things on the market if it succeeds.
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 13:46 UTC (Fri) by Hausvib6 (guest, #70606) [Link]
With both Android and Meego (hopefully not only on Intel), the future of Linux devices!
MIPS Technologies Launches New Developer Community Posted Apr 15, 2011 16:32 UTC (Fri) by jspaleta (subscriber, #50639) [Link]
Hmm. MIPS is spinning up an Android focused effort to compete with ARM in the consumer space. I hope Canonical is taking notice of this. If they don't get on board the MIPS train as its pulling out of the station they going to pretty much cede the first couple of years of whatever MIPS device market develops around this effort to Android. That's really not a good idea if your core customers in your own consumer device push are OEMs/ODMs. If Canonical can't make Ubuntu relevant on MIPS in quick order they'll lose OEM interest as a viable engineering partner.
As Shuttleworth recently said its Canonical or Google now in the device space. Hopefully Canonical can find a way to make it a real competition in the MIPS space (jury is still out on ARM).
-jef
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