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An unexpected perf feature
LWN.net Weekly Edition for May 16, 2013
A look at the PyPy 2.0 release
PostgreSQL 9.3 beta: Federated databases and more
LWN.net Weekly Edition for May 9, 2013
Paul McKenney's parallel programming book
Posted Jan 6, 2011 17:26 UTC (Thu) by etienne (subscriber, #25256)
IHMO there is a need to update a word in another-processor-cache without all the complex code you are using for RCU or counting high frequency events, and without even exchanging the cache line (i.e. in hardware).
Hopefully in next generation CPU, the assembly instruction "post inc eth_counter" will not update local processor flags, and send a request to every cache to update this address - and if no cache has this line to behave like "inc eth_counter"; and use "post or 0x100,rcu_period" to finish a grace period, irrespective of where rcu_period variable is.
It seems to me, if the solution to increase a variable is too complex, it is because the problem is being handled at the wrong level - i.e. a hammer is being used to change the light bulb.
I have written the initial comment before reading "Quick Quiz 4.10", but I still think some millions of those processor's transistor could be used to reduce the number of values a single variable can hold at the same time...
Posted Jan 6, 2011 23:52 UTC (Thu) by cmccabe (guest, #60281)
I'm not sure if an in-hardware lazy update cache would be more difficult to understand or less for developers. In general, application programmers are horrified by the concept of eventual consistency. The problem from their perspective is not the lack of direct hardware support, but the concept itself. Things like SQL were developed so that they wouldn't have to think about these kind of ordering issues.
As long as its just us systems programmers dealing with this stuff, I doubt that Intel or AMD is going to be very motivated to make it "simpler."
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