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Glibc change exposing bugsGlibc change exposing bugsPosted Nov 12, 2010 14:32 UTC (Fri) by Wol (guest, #4433)In reply to: Glibc change exposing bugs by slashdot Parent article: Glibc change exposing bugs
Please define a "backward copy".
Bear in mind Intel processors are arse-about-face (otherwise known as big-endian). Running on a little-endian processor, there is a clear "top" and "bottom". So we can define forwards and backwards.
But on Intel, let's say I want to write the number 1,234,567,890. And my processor has a 3-digit word size. It actually physically exists in the system as 890,567,234,1 ! So where's the top, bottom, front or back?
The other question, of course, is does the address register increment or decrement faster. There's no reason why those two operations should be equal cost (there's no reason why they shouldn't be, either :-) And if they're different, the result will be a difference in speed going forward or backwards.
Cheers,
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Glibc change exposing bugs Posted Nov 15, 2010 9:47 UTC (Mon) by mpr22 (subscriber, #60784) [Link] I must confess to being utterly boggled by the notion of a backwards block copy (decrementing address) being faster than the forward (incrementing address) version. I mean, doesn't backward copying break the memory controller prefetch?
Glibc change exposing bugs Posted Nov 15, 2010 11:50 UTC (Mon) by cladisch (✭ supporter ✭, #50193) [Link]
Backward copying avoids cache address aliasing effects on these processors:
http://lists.freedesktop.org/archives/pixman/2010-August/...
Glibc change exposing bugs Posted Nov 15, 2010 12:15 UTC (Mon) by slashdot (guest, #22014) [Link]
That rationale seems a bit dubious.
In particular, won't just doing all reads before all writes ensure no aliasing regardless of CPU operation?
That is, do this:
Also, their backward copy obviously aliases if rsi is 0xf00c instead of 0xf004. I'm not sure why either of these cases should be intrinsically more frequent.
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