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LWN.net Weekly Edition for May 23, 2013
An "enum" for Python 3
An unexpected perf feature
LWN.net Weekly Edition for May 16, 2013
A look at the PyPy 2.0 release
OK...found the tacnology term: DCA (Direct Cache Access)
One example: http://www.dell.com/downloads/global/products/pwcnt/en/nic-intel-gb-et-brief.pdf
Posted Nov 4, 2010 15:39 UTC (Thu) by i3839 (guest, #31386)
To quote bgoglin:
> DCA doesnt really reduce the memory bandwidth requirements since the
> data still has to be fetched by the cache from the main memory (the
> device doesnt write into the cache, it just tells the cache that data
> should be fetched). The whole point of the approach is that this fetch
> is done in advance, so you dont have to wait for it when the host starts
> processing the packet.
So it doesn't seem that good yet.
With integrated memory controllers I would think it's easy to do this automatically, or at least very easily, by directly going to the cache first instead of through RAM (at least the L3 cache).
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