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ARM's multiply-mapped memory messARM's multiply-mapped memory messPosted Oct 15, 2010 18:34 UTC (Fri) by dlang (✭ supporter ✭, #313)In reply to: ARM's multiply-mapped memory mess by drag Parent article: ARM's multiply-mapped memory mess
that depsnds on exactly how detailed the specs are. I believe that the ARM specs are not behavior (i.e. must implement these commands these ways), but are instead a much lower level (arrange logic gates in this way)
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ARM's multiply-mapped memory mess Posted Oct 15, 2010 22:17 UTC (Fri) by gnb (subscriber, #5132) [Link]
That in turn depends on the licence: most of their customers (sorry, partners) licence an implementation. They get given either synthesizable code or a hard macro that implements the core (+MMU +cache as appropriate) to drop into their chip. Modulo bugs, all chips of this sort with the same core IP should behave the same. A few large partners (Marvell, Ti?) have architecture licences that cover changing the implementation provided it still matches the spec. . In those cases all bets are off for behaviour that the spec. doesn't define.
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