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Random instruction timingsRandom instruction timingsPosted Oct 8, 2009 14:01 UTC (Thu) by jzbiciak (✭ supporter ✭, #5246)In reply to: Random instruction timings by dlang Parent article: Scenes from the Real Time Linux Workshop
The magnitude of an external cache miss is still high enough that I imagine you could see its signature even over the LS-bit noise in the TSC. It may take several runs to correlate things well enough, though, so an isolated encryption event may still hide in the noise.
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